1. Field
Embodiments of the invention relate to memories, and more particularly, to nanocrystal memories.
2. Description of the Related Technology
Nanocrystal memory devices can retain stored information, even when not receiving power. The retention time, programming speed, and erase speed of a nanocrystal memory device can be important design parameters. Reducing the tunnel oxide thickness of a nanocrystal memory device permits integration of nanocrystal memories with scaled-down CMOS platforms. However, a thin tunnel oxide can degrade the retention time of the nanocrystal memory device.
Prior efforts to scale down nanocrystal memory devices have included the use of floating metal nanocrystals, floating Ge nanocrystals, Ge/Si hetero-nanocrystals and porphyrin molecules as charge storage nodes. Other approaches have considered multi-layered dielectrics, including, for example, crested multilayer tunneling barriers and the use of nitride/oxide layered structures to replace a single oxide tunneling barrier. In a further example, quasi-superlattices have been reported, wherein multilevel storage is realized by using a Si/Si3N4 superlattice.
Conventional approaches have required the use of complex fabrication processes, careful material selection, and/or additional masking steps, as compared with a standard Si CMOS process. Moreover, the tradeoffs that exist between extended duration retention and slower programming and erasure speed have not been completely removed.
There is a need for improved nanocrystal memories and methods of forming the same. Moreover, there is a need for nanocrystal memory devices which are compatible with existing Si VLSI processes, and which can function as both p-channel and n-channel memories.